1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a vertical type transistor.
2. Description of Related Art
With the increasing density of a DRAM (Dynamic Random Access Memory), it is becoming difficult to two-dimensionally layout the gate, source, and drain of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) constituting the DRAM. In particular, when the minimum wiring pitch is not more than 90 nm, the above components need to three-dimensionally be laid out.
The MOSFET having a three-dimensional configuration is a transistor having a semiconductor pillar formed on the surface of a semiconductor substrate, first and second diffusion layers formed at the upper portion and at the lower portion of (or below) the semiconductor pillar, and a gate insulating film and a gate electrode covering the side surface of the semiconductor pillar. One of the first and second diffusion layers serves as the source (S) and the other thereof serves as the drain (D). When such a MOSFET is used as a memory cell transistor of the DRAM, the gate electrode is a word line. In such configured transistor, a channel is formed inside the semiconductor pillar in the vertical direction (normal direction of the semiconductor substrate). Thus, hereinafter, such a MOSFET is referred to as “vertical type transistor”.
Japanese Patent Application Laid-Open No. 2008-140996 discloses an example of the vertical type transistor. This vertical type transistor has a pillar body 100e as a semiconductor pillar, upper and lower diffusion layers 107 and 108 formed at the upper portion and below the pillar body 100e, a gate insulating film 106 and a gate electrode 110 formed at the side surface portion of the pillar body 100e. Operation of the vertical type transistor will be described using this example. ON/OFF operation of the vertical type transistor is controlled by the value of voltage applied to the gate electrode 110. When voltage of higher than a threshold value is applied to the gate electrode 110, a channel is formed inside the pillar body 100e to turn ON the vertical type transistor. In an ON state, a charge transfers from one of the upper and lower diffusion layers 107 and 108 to the other one thereof. As a result, drain current flows between the source and drain of the vertical type transistor.
In the semiconductor device, there may be a case where source/drain switching (bias switching) is performed. In a transistor (planar type transistor) in which the gate, source, and drain are two-dimensionally laid out, the magnitude of the drain current does not change before and after the bias switching under normal circumstances; while in the vertical type transistor, the drain current changes before and after the bias switching. This is because the source/drain structure of the vertical type transistor is dissymmetric. A detailed description of this will be given below.
Here, a P-channel type MOS transistor is taken as an example. The magnitude of the drain current of the transistor depends upon the P-type impurity concentration of a source side diffusion layer. This is because the hole density of a channel inversion layer depends upon the P-type impurity concentration of a source side diffusion layer.
In the vertical type transistor, in a forward bias state (state where the drain current flows from the lower diffusion layer to upper diffusion layer), the lower diffusion layer serves as the source side diffusion layer, so that the magnitude of the drain current depends upon the impurity concentration of the lower layer diffusion layer. On the other hand, in a reverse bias state (state where the drain current flows from the upper diffusion layer to lower diffusion layer), the upper diffusion layer serves as the source side diffusion layer, so that the magnitude of the drain current depends upon the impurity concentration of the upper layer diffusion layer.
In the case where a diffusion layer is formed by a typical ion-implantation method, the impurity concentration of the diffusion layer is proportional to the ion-implanted area. In the planer type transistor, it is easy to make the areas of two diffusion layers substantially equal to each other. This can prevent the two diffusion layers from differing in the impurity concentration. On the other hand, in the vertical type transistor, it is difficult to make the dimension of the entire semiconductor pillar constant from the upper to lower portions thereof, so that the area of the upper diffusion layer positioned at the upper portion of the semiconductor pillar and area of the lower diffusion layer positioned at the lower portion of (or below) the semiconductor pillar inevitably differ from each other. This is the reason that the magnitude of the drain current changes before and after the bias switching in the vertical type transistor.
Although the vertical configuration is suitable for some type of the transistor or some purpose, it is likely that the change in the drain current associated with the bias switching is unfavorable. Thus, a vertical type transistor in which the magnitude of the drain current does not change before and after the bias switching is required.